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Datasheet

GAL20VP8B-25LJ

Manufacturer

Lattice

Model

GAL20VP8B-25LJ

Category

special_chips

›control_chips

›Programmable Logic Device (CPLD/FPGA)

Reference Pricing

1+ :$3.2928

200+ :$1.4812

500+ :$1.3706

1000+ :$1.4784

Reference Stock

Available:Unknown

Specifications

Clock Frequency	Fmax = 80 MHz
Memory Capacity	Not specified
Number of Logic Gates	64
Operating Temperature Range	Not specified
Operating Voltage	Not specified
Package Type	PLCC-28(11.5x11.5)
Peripheral Interfaces	Schmitt trigger inputs, programmable open-drain or Totem-Pole outputs, active pull-ups on all input and I/O pins
Pin Count	28
Power Consumption	90mA - 115mA
Programmable Resources	10.0% tested, 100% yields
Programming Method	E2 Cell Technology, high-speed electrical erase (<100ms), 20-year data retention

Datasheet

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