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Datasheet

GAL16VP8B-15LP

Manufacturer

Lattice

Model

GAL16VP8B-15LP

Category

special_chips

›control_chips

›Programmable Logic Device (CPLD/FPGA)

Reference Pricing

1+ :$3.2074

200+ :$1.3482

500+ :$1.1046

1000+ :$1.358

Reference Stock

Available:Unknown

Specifications

Clock Frequency	80 MHz
Memory Capacity	Not specified
Number of Logic Gates	64
Operating Temperature Range	0°C to 70°C
Operating Voltage	2.0V to 5.5V
Package Type	PDIP-20
Peripheral Interfaces	Schmitt trigger inputs, programmable open-drain or Totem-Pole outputs, active pull-ups on all input and I/O pins
Pin Count	20
Power Consumption	90mA to 115mA
Programmable Resources	10.0% tested, 100% yield
Programming Method	E2 Cell Technology

Datasheet

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